This invention relates to a method for manufacturing a semiconductor device and a semiconductor device technique, and more particularly relates to a technique that is effectively applied to a technique for manufacturing a semiconductor device having a bipolar transistor with so-called self-alignment type or HBT (Hetero-junction Bipolar Transistor) structure, which have a base layer formed by use of selective epitaxial growing technique.
The self-alignment type bipolar transistor technique, in which a base layer of a bipolar transistor is formed by use of selective epitaxial growing technique, has been developed to improve the high speed performance of a bipolar transistor. For example, Japanese Unexamined Patent Publication No. Hei 6(1994)-112215 discloses a self-alignment type bipolar transistor technique. One example of a method for forming a self-alignment type bipolar transistor will be described herein under.
At first a shallow groove is formed on a semiconductor substrate for element separation. Thereafter, a silicon oxide film, a p-type polycrystalline silicon film, and a silicon nitride film are deposited on the semiconductor substrate by mean of CVC (Chemical Vapor Deposition) technique in the order from the bottom. Subsequently, the silicon nitride film and the p-type polycrystalline silicon film are dry etched to form an emitter aperture. Thereafter a silicon nitride film is formed by means of CVD technique, and then the silicon nitride film is subjected to etch back to form a side wall comprising the silicon nitride film on the side wall of the emitter aperture. At that time, CHF base gas is used as the etching gas because of the selectivity of the silicon oxide film. Next, the silicon oxide film on the bottom of the emitter aperture is subjected to wet etching by use of the silicon nitride film and the side wall as a mask. At that time, the silicon oxide film located just under the side wall and under the p-type polycrystalline silicon film is etched to form an under cut portion. Next, for example, a p-type epitaxial SiGe layer is formed on the portion in the emitter aperture where the semiconductor substrate surface and the polycrystalline silicon film are exposed by means of selective epitaxial growing technique. At that time, the under cut portion located just under the polycrystalline silicon film is embedded in the SiGe layer, and the p-type polycrystalline silicon film is connected to the SiGe layer. Furthermore, an n+-type polycrystalline silicon film is formed to form an emitter polycrystalline silicon electrode. Thereafter, impurity is thermally diffused from the n+-type polycrystalline silicon layer to form an n+-type emitter region on the SiGe layer.